The present invention relates to clock signal switching devices, clock signal switching methods, data bus switching devices, and data bus switching methods. The present invention more particularly relates to clock signal switching devices and clock signal switching methods for selecting one from among a plurality of clock signals in data receiving devices, and also relates to data bus switching devices and data bus switching methods for selecting, in data receiving devices, one from among data signals inputted via a plurality of data buses.
In recent years, receiving devices which receive data sets from a plurality of transmission paths and output one of the received data sets have been widely used in systems for transmitting video signals, audio signals, and other signals. Those receiving devices need a transmission path switcher for selecting a transmission path.
For example, some analog TV monitors can receive data sets outputted from a plurality of transmitting devices such as a video player and a DVD player, and also perform switching among those received data sets to display a selected data.
Hereinafter, a description of three exemplary prior-art receiving devices will be made, which can perform switching among data sets received via a plurality of transmission paths and output the selected data.
FIG. 46A illustrates an example of a first prior art device capable of outputting any one of a plurality of inputted analog signals in its original analog signal form. FIG. 46B illustrates an example of a second prior art device capable of converting a plurality of inputted digital signals into analog signals and then outputting any one of the analog signals.
As shown in FIG. 46A, the first prior art device 1 includes an analog signal switcher 2, which can select any one of a plurality of inputted analog signals (two kinds of analog signals in FIG. 46) and output the selected analog signal in its original analog signal form.
Also, as shown in FIG. 46B, along with recent increased usage of digital signals, the second prior art device 3, which can convert a plurality of inputted digital signals into analog signals and output any one of the converted analog signals, has also been commonly used. The second conventional device 3 is furnished with a plurality of DACs (digital to analog converters) 4 that convert the plurality of inputted digital signals into the respective analog signals, and an analog signal switcher 5 that outputs any one of the analog signals converted by the DACs 4.
However, the first conventional device 1 shown in FIG. 46A, which switches the multiple analog signal inputs, is adversely affected by noise that is peculiar to analog signals. Also, in the second prior art device 3 shown in FIG. 46B, in which digital signals have to be converted into analog signals, accurate reproduction of the inputted data as it is might become difficult depending on the accuracy of the conversion into the analog signals performed by the DACs 4.
In view of these problems, a third prior art device, which is capable of outputting an inputted digital signal in its original digital signal form, has been proposed as a result of recent advancement of digital technology. FIG. 46C illustrates such a third prior art device.
FIG. 46C illustrates an example of the third prior art device that can output any one of a plurality of inputted digital signals in its original digital signal form.
As shown in FIG. 46C, the third prior alt device 6 is provided with a digital signal switcher 7, which selects any one of a plurality of inputted digital signals and outputs the selected digital signal in its original digital signal form. Therefore, for example, when the third conventional device 6 is installed in a television monitor such as a digital flat panel, the television monitor becomes able to display received digital signals without converting those digital signals into analog signals. Since such conversion to analog signals is not necessary, the received original digital images and other data can be reproduced highly accurately. Furthermore, unlike the second prior art device 3, the third prior art device 6 does not need to include DACs 4 that convert digital signals into analog signals. This results in a reduction in the size of the receiving device itself.
Nevertheless, if the third prior art device 6 shown in FIG. 46C employs a system such as DVI (digital visual interface) or HDMI (high definition multimedia interface) for transmitting video signals and audio signals, a clock signal for adjusting the timing of transmitting/receiving of the data signals such as the video and audio signals has to be transmitted separately from those data signals. In that case, a receiving device such as the third prior art device 6, e.g., operates based on the timing of such an inputted clock signal. Thus, if the clock signal is disturbed, the data signals might not be processed properly. In addition, transmission systems such as DVI and HDMI have specifications by which clock signals with different phases or different periods can be transmitted/received. Just switching over from one inputted clock signal to another in the receiving device may therefore lead to occurrence of a short-width abnormal pulse (a hazard), duty ratio breakdown, or other disturbance in the clock signal. Such a disturbance in the clock signal becomes a critical problem particularly in specifications such as DVI or HDMI by which clock signals can be switched. Therefore, digital transmission systems that transmit data signals and clock signals separately require a system that prevents clock signal disturbance when clock signals are switched.
As a means for solving the above problem, the Japanese Laid-Open Publication No. 9-98161, for example, discloses a synchronous clock signal switching circuit. More specifically, the synchronous clock signal switching circuit disclosed in the publication is designed in the following manners to prevent occurrence of a hazard or duty ratio breakdown in a newly selected clock signal.
First, as a means for preventing occurrence of a hazard (or a glitch) in a clock signal, a clock signal selection signal (a switching signal), which is inputted when an inputted first clock signal and an inputted second clock signal are both at a high level, is synchronized with a falling edge of the logical product of the first and second clock signals. In this case, either the first or second clock signal is selected and outputted based on the clock signal selection signal that is synchronized with the falling edge of the logical product of the first and second clock signals.
Also, in order to avoid duty ratio breakdown (a pulse jump) in the clock signal, when switchover from the inputted first clock signal to the inputted second clock signal is performed, a phase difference between the first and second clock signals is detected. If the detected phase difference is greater than ±90°, switchover to the inverted second clock signal is performed. On the other hand, if the detected phase difference is smaller than ±90°, switchover to the inputted second clock signal in its original state is performed.